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RM0008
Note:
Universal serial bus full-speed device interface (USB)
clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different
from the clock used for the interface to the APB1 bus. Different clock configurations are
possible where the APB1 clock frequency can be higher or lower than the USB peripheral
one.
Due to USB data rate and packet memory interface requirements, the APB1 clock frequency
must be greater than 8 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the USB_BTABLE register. Each
table entry is associated to an endpoint register and it is composed of four 16-bit words so
that table start address must always be aligned to an 8-byte boundary (the lowest three bits
of USB_BTABLE register are always “000”). Buffer descriptor table entries are described in
the Section 21.5.3: Buffer descriptor table . If an endpoint is unidirectional and it is neither an
Isochronous nor a double-buffered bulk, only one packet buffer is required (the one related
to the supported transfer direction). Other table locations related to unsupported transfer
directions or unused endpoints, are available to the user. isochronous and double-buffered
bulk endpoints have special handling of packet buffers (Refer to Section 21.4.4: Isochronous
transfers and Section 21.4.3: Double-buffered endpoints respectively). The relationship
between buffer description table entries and packet buffer areas is depicted in Figure 191 .
Figure 191. Packet buffer areas with examples of buffer description table locations
B u ffer for
do ub le- bu ffered
IN Endpoint 3
0001_1110 (1E) COUNT 3 _TX_1
0001_1100 (1C) ADDR 3 _TX_1
0001_1010 (1A) COUNT 3 _TX_0
0001_1000 (1 8 ) ADDR 3 _TX_0
0001_0110 (16) COUNT2_RX_1
0001_0100 (14) ADDR2_RX_1
0001_0010 (12) COUNT2_RX_0
0001_0000 (10) ADDR2_RX_0
0000_1110 (0E) COUNT1_RX
B u ffer for
do ub le- bu ffered
OUT Endpoint 2
Tr a n s mi ss ion
bu ffer for
s ingle- bu ffered
0000_1100 (0C)
0000_1010 (0A)
0000_1000 (0 8 )
0000_0110 (06)
0000_0100 (04)
0000_0010 (02)
0000_0000 (00)
ADDR1_RX
COUNT1_TX
ADDR1_TX
COUNT0_RX
ADDR0_RX
COUNT0_TX
ADDR0_TX
Endpoint 1
Reception bu ffer
for
Endpoint 0
Tr a n s mi ss ion
bu ffer for
Endpoint 0
B u ffer de s cription t ab le loc a tion s
P a cket bu ffer s
a i17109
Each packet buffer is used either during reception or transmission starting from the bottom.
The USB peripheral will never change the contents of memory locations adjacent to the
Doc ID 13902 Rev 9
517/995
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